mallet algirithm

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)

ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users

一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！-A simple shift register. VHDL language, and perhaps will help you!

1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

自动售货机程序(Vending machine procedures)

SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)

Interfacing RTC with spartan 3

利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。

四分频的程序，输出clkout0就是二分频，clkout1是四分频-Quarter-frequency process, the output clkout0 is two-way, clkout1-fourth the frequency