ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)

Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.

一种能简单的实现I2C通讯的代码，对于主机和从机之间的通讯讲解的很清楚。(A Code for I2C Communication)

对ccd图像进行解码采集，并通过VGA输出(Ccd image decoding of the collection, and through the VGA output)

DSP28335与FPGA通过spi通信，此程序为28335为主接收程序(DSP28335 and FPGA through the SPI communication, this procedure for the 28335 receiving procedures)

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)

VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only

说明：  基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)

modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!