登录
首页 » VHDL » 输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...

输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...

于 2023-02-24 发布 文件大小:6.31 kB
0 164
下载积分: 2 下载次数: 1

代码说明:

输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2-a afdg jhg dfgh r fbnrfer

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 用Verlog HDL编写的数字钟程序,包含时,分,秒,进位,解码,扫描显示等功能。...
    用Verlog HDL编写的数字钟程序,包含时,分,秒,进位,解码,扫描显示等功能。-Written by Verlog HDL ,a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
    2023-02-05 04:55:03下载
    积分:1
  • PC
    说明:  Verilog HDL语言编写的32位程序计数器(PC)完整工程及相应仿真,QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)
    2012-09-06 09:07:47下载
    积分:1
  • cn60
    六十进制计数器用于计数等操作,代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)
    2014-12-10 10:10:50下载
    积分:1
  • uartfifo
    串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。(uart communication)
    2017-04-20 22:16:21下载
    积分:1
  • uart_test
    说明:  用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)
    2019-03-13 14:15:24下载
    积分:1
  • This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
    这是一个用VHDL语言编写的并口转串口程序,在altera开发系统下验证通过,运用于开发板与计算机之间的通信,源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
    2022-03-23 13:41:19下载
    积分:1
  • 遥控器接收解码电路
    设计遥控器接收解码电路。该电路接收编码后的串行数据,解码输出数据。电路接收 到的串行数据的格式为: 4 位同步码“ 1010”, 4 位数据(高位在前), 1 位奇校验码(对前 8 位数据校验)(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))
    2017-11-27 15:10:34下载
    积分:1
  • ALU_4bit
    4位ALU,有两个4位输入,4位输出实现逻辑运算和算术运算,逻辑与或非,加1,减1等等功能(4 ALU, logical and arithmetic operations)
    2012-11-18 18:04:59下载
    积分:1
  • 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计,包括偶数分频、非 50%占空比和 50%占空比的奇数分频、半整数 (N+0...
    本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计,包括偶数分频、非 50%占空比和 50%占空比的奇数分频、半整数 (N+0.5)分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合,形成可使 用的电路,并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
    2022-08-24 20:51:04下载
    积分:1
  • UART_prj_ViHDL
    vhdl project at sbu uni in iran uart
    2010-05-08 16:18:37下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载