输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...

说明：  lab report for lab 4

用verilog hdl写的Norflash控制器，可实现单字节读写，扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

七段LED数码管显示译码器设计，将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)

经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器

讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)

ac97 VHDL core

说明：  对于有经验的用户和新用户写的，这本书给您的Verilog HDL的广泛报道。该书强调了实际设计和验证的角度，而不是只注重Verilog的语言方面。(Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. )

数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)

小波提升算法源码，里面一个txt文件可以当作算法参考；(Wavelet lifting algorithm source code, inside a TXT file can be used as algorithm reference;)