输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...

说明：  Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)

利用ITU656接口传输数据流的方法!已得到应用!(ITU656 interface transfer data streams using the method! Has been applied!)

PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)

vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧-vga display code, which has ise project file is transferred directly past, everyone download it

在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector

说明：  良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)

说明：  基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)

四线电阻式触摸屏，ads7846控制显示触摸坐标(Four-wire Resistive Touch Panel, ads7846 touch control display coordinates)