verilog例子，有130多个，值得参考，新手很有帮助

OFDM modulation source code written in Matlab

VHDL实现的超前进位加法器-the VHDL-ahead Adder

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

FIR滤波器：自定滤波器的类型（低通，高通或带通）、设计指标（通带截止频率、通带波纹、阻带截止频率、阻带衰减） 1、根据指标选择合适的窗函数，用窗口设计法设计符合指标的FIR滤波器；并验证其性能是否满足预定指标。 (FIR filters: Custom filter types (low pass, high pass or band-pass), design specifications (passband cutoff frequency, passband ripple, stopband cutoff frequency, stopband attenuation) 1, according to indicators choose the right window function, using the window design method of FIR filter designed to meet the targets and verify that its performance meets the set targets.)

BT656转RGB的算法实现代码，使用VORILOG语言编写(BT656-->RGB, verilog)

csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

design ram v8051 for project

ep2c5 实现 段寄存器 verilog语言，quartus 2 仿真-the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation