verilog例子，有130多个，值得参考，新手很有帮助

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

VHDL Vendingmachine source

说明：  fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)

利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer

说明：  PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)

说明：  asssembly ccode to turn on 7 segmen

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

用verilog编写的1024点的fft快速傅立叶变换-Verilog prepared using 1024 point fft Fast Fourier Transform

SDIO slave verilog code

it will count the bit