基于Verilog的FFT核

在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)

说明：  一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)

个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)

能实现数字钟中时间的显示，并可对小时，分钟，秒进行调整-Can realize the time digital clock display, and on the hours, minutes, seconds to adjust

combinatorial modules

Control Unit VHDL code. Xilinx Spartan 3E board

用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

verilog实现的串口实现代码，可以直接复制使用(verilog achieve serial implementation code can be copied directly use)

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen