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脉动进位加法器
设计的结构是纹波进位加法器,但执行的操作是加法和减法,两种操作都是32位的,具体取决于控制信号。如果控制信号为“1”,则选择减法,然后选择“0”,然后选择加法
- 2022-02-02 17:58:16下载
- 积分:1
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power_control
四轴动力模块,用一个顶模块控制,输入有:油门(20档);指令;水平仪控制指令,4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)
- 2013-12-26 20:57:03下载
- 积分:1
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Altium Partner SN-1000010 r10
Browser modularization processing, browser modularization combing, browser modularization expansion
- 2020-06-24 04:20:01下载
- 积分:1
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程序采用VHDL:频率合成DDS主要调用LPM,
程序用VHDL实现:
频率合成,DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分:1
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lab7_files
关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)
- 2013-02-01 11:02:38下载
- 积分:1
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Encoder_SSI_Veryilog
说明: 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯(SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementation of the communication with the absolute encoder)
- 2020-12-28 20:59:02下载
- 积分:1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分:1
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用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
- 2023-05-23 03:15:03下载
- 积分:1
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PWM for control of motors
PWM for control of motors
- 2022-07-25 05:36:51下载
- 积分:1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分:1