基于Verilog的FFT核

H.264中二进制算术编码的硬件实现Binary arithmetic coding in H.264 hardware implementation(Binary arithmetic coding in H.264 hardware implementation)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

说明：  Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

说明：  FFT 1024 point, in 10 state

Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具， 各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 (FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.)

verilog编写的DAC2902程序，用于高速的数模转换(verilog language,using for DAC2902 digital analog converter)

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．-Verilog realize traffic lights, with detailed notes in Chinese.