用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！...

基于CPLD的交通灯控制，完成交通灯的功能，校错能力(CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity)

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)

veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.

基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02

四位数字乘法器，在quartus8.0下仿真时序图 -mult4

mux one hwich is teh best knwo progerma i n the workdl and ist is the

自动售货机的状态机实现 自动售货机的状态机实现(this is a automachine)

verilog program for real time clock.. select the .v file to view the code.