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addsub32bit
32bit floating point addition
- 2021-04-06 18:19:02下载
- 积分:1
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frame_syn
通信系统中数据的传输以帧为单位,在FPGA中帧头检测是通信系统中的一部分,该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)
- 2014-08-27 16:02:54下载
- 积分:1
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verilog
用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)
- 2021-04-25 20:48:46下载
- 积分:1
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FRFT_Ozaktas
这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序,FPGA是Xilinx的virtecx-5,这是我在做毕业设计的时候自己编写的,希望能对你有帮助!(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)
- 2021-03-12 10:49:25下载
- 积分:1
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designers guide to vhdl(third edition)
说明: designers guide to vhdl(third edition)这本书好像在国外vhdl入门中挺流行的, 爱思维尔有资源,但是是各个章节散装的, 我把它们合成了(The book designers guide to vhdl (third edition) seems to be very popular in foreign vhdl entry. Ixel has resources, but it is a loose chapter of each chapter, I synthesized them)
- 2021-01-14 16:23:11下载
- 积分:1
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fenpin
这是一个二进制的最简单分频器,是一个简短的fpga代码,用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分:1
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光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考...
光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
- 2022-04-20 02:09:46下载
- 积分:1
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系统设计
基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)
- 2020-06-21 02:00:01下载
- 积分:1
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16-bit-CPU
单周期16位CPU的设计,我们的计算机组成原理课设,可以实现R型、I型和J型指令,内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)
- 2020-08-02 10:28:35下载
- 积分:1
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波特率选择VHDL源代码没有错误调试
波特率可供选择的vhdl源程序,已调试无错误-Baud rate options VHDL source code has no error debug
- 2022-04-25 04:22:33下载
- 积分:1