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Matrix_inv

于 2017-04-24 发布 文件大小:22068KB
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代码说明：

  基于fpga的矩阵求逆运算，适用xilinx v6板卡(Inverse operation based on fpga matrix)

文件列表：

Matrix_inv
..........\code
..........\....\chg_dir.v,837,2017-03-25
..........\....\chg_dir2.v,2648,2017-03-26
..........\....\importdata.v,3601,2017-04-08
..........\....\importdata.v.bak,3626,2017-03-30
..........\....\importdatb.v,3728,2017-04-08
..........\....\importdatb.v.bak,3753,2017-03-30
..........\....\inop.v,845,2017-03-25
..........\....\inv_unit.v,5281,2017-03-30
..........\....\lu_unit.v,2705,2017-03-24
..........\....\mult_unit.v,1560,2017-03-30
..........\....\pe2_unit.v,4233,2017-03-26
..........\....\pe_unit.v,4029,2017-03-30
..........\....\tb
..........\....\..\test_tb.v,2019,2017-04-01
..........\data
..........\....\creat_data.m,681,2017-04-01
..........\....\matrix.txt,84,2017-04-01
..........\....\vector.txt,84,2017-04-01
..........\ip
..........\..\fixed_2_flt.v,167248,2017-03-23
..........\..\flt_2_fixed.v,161677,2017-03-23
..........\..\flt_add.v,282626,2017-03-23
..........\..\flt_div.v,829565,2017-03-23
..........\..\flt_mult.v,206169,2017-03-23
..........\sim
..........\...\glbl.v,1366,2012-12-05
..........\...\simulate_mti.do,461,2017-04-08
..........\...\view_result.do,1488,2017-04-01
..........\...\work
..........\...\....\chg_dir
..........\...\....\.......\verilog.asm64,15872,2017-04-08
..........\...\....\.......\verilog.rw64,502,2017-04-08
..........\...\....\.......\_primary.dat,1251,2017-04-08
..........\...\....\.......\_primary.dbs,1028,2017-04-08
..........\...\....\.......\_primary.vhd,431,2017-04-01
..........\...\....\chg_dir2
..........\...\....\........\verilog.asm64,39808,2017-04-08
..........\...\....\........\verilog.rw64,2293,2017-04-08
..........\...\....\........\_primary.dat,3310,2017-04-08
..........\...\....\........\_primary.dbs,3035,2017-04-08
..........\...\....\........\_primary.vhd,433,2017-04-01
..........\...\....\fixed_2_flt
..........\...\....\...........\verilog.asm64,1353056,2017-04-08
..........\...\....\...........\verilog.rw64,2061,2017-04-08
..........\...\....\...........\_primary.dat,186895,2017-04-08
..........\...\....\...........\_primary.dbs,136318,2017-04-08
..........\...\....\...........\_primary.vhd,450,2017-04-01
..........\...\....\flt_2_fixed
..........\...\....\...........\verilog.asm64,1287392,2017-04-08
..........\...\....\...........\verilog.rw64,471,2017-04-08
..........\...\....\...........\_primary.dat,181294,2017-04-08
..........\...\....\...........\_primary.dbs,131214,2017-04-08
..........\...\....\...........\_primary.vhd,450,2017-04-01
..........\...\....\flt_add
..........\...\....\.......\verilog.asm64,2124624,2017-04-08
..........\...\....\.......\verilog.rw64,2706,2017-04-08
..........\...\....\.......\_primary.dat,302214,2017-04-08
..........\...\....\.......\_primary.dbs,214109,2017-04-08
..........\...\....\.......\_primary.vhd,759,2017-04-01
..........\...\....\flt_div
..........\...\....\.......\verilog.asm64,6967088,2017-04-08
..........\...\....\.......\verilog.rw64,2510,2017-04-08
..........\...\....\.......\_primary.dat,943625,2017-04-08
..........\...\....\.......\_primary.dbs,703086,2017-04-08
..........\...\....\.......\_primary.vhd,591,2017-04-01
..........\...\....\flt_mult
..........\...\....\........\verilog.asm64,1437984,2017-04-08
..........\...\....\........\verilog.rw64,2489,2017-04-08
..........\...\....\........\_primary.dat,206304,2017-04-08
..........\...\....\........\_primary.dbs,145823,2017-04-08
..........\...\....\........\_primary.vhd,593,2017-04-01
..........\...\....\glbl
..........\...\....\....\verilog.asm64,25040,2017-04-08
..........\...\....\....\verilog.rw64,1036,2017-04-08
..........\...\....\....\_primary.dat,1524,2017-04-08
..........\...\....\....\_primary.dbs,1624,2017-04-08
..........\...\....\....\_primary.vhd,351,2017-04-01
..........\...\....\importdata
..........\...\....\..........\verilog.asm64,242032,2017-04-08
..........\...\....\..........\verilog.rw64,1943,2017-04-08
..........\...\....\..........\_primary.dat,4754,2017-04-08
..........\...\....\..........\_primary.dbs,2980,2017-04-08
..........\...\....\..........\_primary.vhd,493,2017-04-01
..........\...\....\importdatb
..........\...\....\..........\verilog.asm64,229056,2017-04-08
..........\...\....\..........\verilog.rw64,2004,2017-04-08
..........\...\....\..........\_primary.dat,4801,2017-04-08
..........\...\....\..........\_primary.dbs,2947,2017-04-08
..........\...\....\..........\_primary.vhd,542,2017-04-01
..........\...\....\inop
..........\...\....\....\verilog.asm64,15840,2017-04-08
..........\...\....\....\verilog.rw64,501,2017-04-08
..........\...\....\....\_primary.dat,1282,2017-04-08
..........\...\....\....\_primary.dbs,1022,2017-04-08
..........\...\....\....\_primary.vhd,425,2017-04-01
..........\...\....\inv_unit
..........\...\....\........\verilog.asm64,603408,2017-04-08
..........\...\....\........\verilog.rw64,1918,2017-04-08

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