电子打铃器 在max plus 2 下编译通过

内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)

说明：  mojo v3 complete eagle schematic

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)

基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)

说明：  彩色TFT液晶显示控制电路设计及其ASIC实现(TFT color LCD control circuit design and ASIC realization)

the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)