指令式ROM核

以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation

一个数码管的驱动开发程序，程序完备，可以直接使用，在开发板上使用时注意改变引脚(A digital control of the driver development program, the program is complete, can be used directly, when used in the development of attention to change the pin board)

16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!

wallace tree multiplier in verrilog

USB245I的基于FPGA的VHDL语言的驱动程序,应该有用-USB245I based FPGA VHDL of the driver, should useful

如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)

说明：  QSPI_FLASH_MODEL 可以设计时前端仿真使用(QSPI?_Flash_Model can be used in front-end simulation at design time)

说明：  4位二进制加法计数器的两种不同VHDL的描述,与比较。(4-bit binary addition of two different counter VHDL description, and more.)