指令式ROM核

以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)

初学ＶＨＤＬ有用的，了解后对复杂设计有很大帮助．-VHDL beginner useful understanding of the complexity of the design has been inspired by them.

OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)

FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )

用VHDL语言编程完成数码管0-255数字的显示-VHDL language programming with the 0-255 number to complete the display of the digital control

I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用(I2C bus protocol Verilog source code. Tried, no errors! Can be used directly)

自动打铃系统 附带时钟 定时打铃 整点打铃-Auto-play Ling System

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

说明：  学习使用quartus modelsim(learn to uee quartus modelsim)

一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)