vhdl code for decoder and detemines the basic mechanism of gates of decoder

ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)

音乐计算器，可实现999以下加减法及与非运算功能，并能够播放两段音乐，可下载到FPGA板子上实现。(Music Calculator)

ULPI UTMI conversion

循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)

VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit

基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.

用来检查FPGA通过PHY发送数据时是否有掉帧的现象(FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.