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计数器,vhdl,调试通过。
COUNTER 用于xilinx硬件,里面已建工程,修改ucf即可。设计由3部分组成,计数器,100M分配时钟,顶层模块,其中顶层模块包括计数器和分频器。
- 2022-01-22 06:17:06下载
- 积分:1
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hand_shake
握手程序,可以完美实现跨时钟域的数据传输(handshake and testbench,verilog HDL)
- 2011-11-22 21:05:38下载
- 积分:1
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soble
基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
- 2017-08-30 16:06:04下载
- 积分:1
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FPGA-a-CPLD-newest-Technology-guide
FPGA/CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA/CPLD为主,详细介绍了FPGA/CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog/VHDL语言,并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例,由浅入深地详述了如何应用FPGA/CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证,读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性,力求通俗易懂。
本书适用于计算机、电子、控制及信息等相关专业的在校大学生,对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)
- 2013-08-27 11:39:27下载
- 积分:1
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FFT_16
FFT快速傅立叶变换-verilog,基于verilog的FFT源码,QuartusII上仿真通过(FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation)
- 2020-09-08 20:28:02下载
- 积分:1
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基于basys2的四位有符号二进数除法
基于diligent公司的basys2开发板的四位有符号二进制数的除法
- 2023-08-01 03:30:03下载
- 积分:1
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中值滤波算法
中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法,搭建出完整的数据处理系统架构,通过仿真和验证来判断数据的处理效果,并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)
- 2018-05-30 13:44:03下载
- 积分:1
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Spartan-3E_Starter_Kit
Spartan® -3E 现场可编程门阵列家族是为满足对成本敏感的消费电子大量应用的需要
而特别设计的。
(Field Programmable Gate Array family needs is to meet the cost-sensitive applications, a large number of consumer electronics
Specially designed.)
- 2014-07-10 21:30:34下载
- 积分:1
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mimasuo
密码锁 vhdl实现的密码锁 控制程序-mimasuo
- 2022-02-11 23:21:28下载
- 积分:1
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至于FSK调制原理就不多说了,这里做的一个实验是二进制频移键控。发送一组码元,通过响应的键控电路监测是发1还是发0然后选择频率控制正余弦电路波形。...
至于FSK调制原理就不多说了,这里做的一个实验是二进制频移键控。发送一组码元,通过响应的键控电路监测是发1还是发0然后选择频率控制正余弦电路波形。-see
- 2022-05-23 04:28:41下载
- 积分:1