修改后的展位乘法的两个华莱士算法签名和签名二进制数

将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)

自己在ISE下用VHDL写的UART，简单，易懂(in ISE using VHDL was the UART, simple, understandable)

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

VHDL 波形防止抖动程序,学习试验材料(VHDL prevent jitter waveform procedures, the pilot study materials)

FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

针对京微雅阁的CME300 FPGA教程，里面有几个例程，并附有源代码，初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)

To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.

this is a Multiplier and Accumulate (MAC). written in VHDL