32位ALU

基于FPGA的verilog语言描述五子棋游戏中的棋框显示，应用VGA显示原理，用不同的颜色显示边框。以及根据棋子输入的要求，显示相应的棋子，不同的颜色显示不同的棋框和棋子

基于nios ii 驱动altera de1开发板上的lcd和ps2鼠标模块工程-based on the nios ii drive the lcd and ps2 module of altera de1 develop board

FPGA设计全流程－软件综合使用、 -FPGA design of the whole process- the integrated use of software, FPGA design of the whole process- the integrated use of software,

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)

说明：  1、SignalTap II Logic Analyzer使用方法； 2、掌握捕获条件的设置 3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer; 2. Master the setting of capture conditions 3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)

高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

led 发送卡代码(led send card verilog)

用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )