FPGA UART的发送等

基于Verilog的数码管模拟扫描程序，分为两种显示方式，一种是数码管逐个显示，另一个是所有数码管一起显示。-Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve

Xilinx Licenses 2018

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).

用FPGA实现pwm调制波，通过单片机软核控制输入量来实现任意占空比方波的产生-wave