FPGA UART的发送等

1、掌握WALSH码产生的原理和WALSH码的特性。 2、掌握WALSH码的产生和特性分析的软件仿真。 3、掌握WALSH码的硬件产生方法。 (1, master code WALSH WALSH code generation principles and characteristics. 2, master WALSH code generation and characterization of the software simulation. 3, master code WALSH hardware generation approach.)

带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

设计一4位比较器,画出门级电路图,用verilog语言完成设计。 (Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )

Construction and Experimental Evaluations of User-Centered Power

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.

这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem )

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

FSK模拟信号源，利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)