对于Spartan 3E VGA控制器

xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)

MPEG-2TS 流嵌入控制数据的设计，设计的要求是用控制数据替换MPEG-2 TS 流中的空帧-MPEG-2TS control data stream embedded in the design, the design requirements is to control data to replace MPEG-2 TS stream of the air frame

说明：  asssembly ccode to turn on 7 segmen

altera 的reed solomn 设计(reed solomn design from altera)

ALU using VHDL project

MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative

dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)

3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging

i2c总线的工程实现，可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment