对于Spartan 3E VGA控制器

帧同步的VHDL程序源代码，巴克码同步实现。(Frame synchronization of the VHDL source code, Barker code synchronization)

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

hdlc协议的封装与解析，fsc校验，完整的例程代码(Decode and Encode an HDLC packet ，using FCS16 calculation)

用VHDL语言仿真交通灯 用VHDL语言仿真交通灯-Simulation using VHDL language VHDL language with traffic lights traffic lights Simulation

VHDL与Verilog的比较-VHDL and Verilog comparison

8051核的vhdl原代码。-8051 core VHDL source code.

用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM，代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)

说明：  用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example