FIR滤波器的VHDL语言实现

cadence verilog reference

Efficient_Digital_Implementation_of_Extreme_Learning_Machines_for_Classification

Description of a sistolic arhictecture for a FFT implementation in FPGA.

对原信号进行拉格朗日插值运算，实现信号重采样(The original signal Lagrange interpolation operation, to achieve signal resampling)

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

this is the vhdl code for the arithmetic logic unit.enjoy!

这是一个基本的ARM7_Core 有基本功能 但不是太完善-This is a basic ARM7_Core has the basic functions, but not too perfect

WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)

Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,