实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。...

该计数器可以实现从0到1000的技术，程序简练执行效率高(counter1000)

Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver

基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。-Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and time.

设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure

一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！-A simple shift register. VHDL language, and perhaps will help you!

产生SH,SP,RS,SP,φ1,φ2驱动脉冲，用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)

SystemVerilog For Design (Springer-2nd_Ed-2006)

uart串口的vhdl语言程序。本人调试过 ，非常好用-serial UART VHDL Language Program. I debug, and very easy to use

1. 一位全加器设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY add IS PORT(a,b,cin:IN STD_LOGIC; Co,S:OUT STD_LOGIC); END ENTITY add; ARCHITECTURE fc1 OF add is BEGIN S