实光电码盘的输出数据的四倍频，使码盘输出精度提高四倍。...

本代码来自老师指导，自己编写，可以修改交通灯的时间

说明：  基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程(Quartus ? II related language detailed introduces the verilog VHDL software development process )

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.

直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation

8051核的vhdl原代码。-8051 core VHDL source code.

FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

基于CPLD的38译码器程序设计，使用VHDL语言编程，38译码器显示在数码管上。

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)