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Synopsys-tools-intruction
synopsys的主要的工具介绍,包括DC,PT,Formality等,对于初学IC设计者了解设计工具有很大帮助。(synopsys of the main tools for presentations, including DC, PT, Formality, etc., for the beginner tool for IC designers to understand the design of much help.)
- 2011-08-06 12:21:01下载
- 积分:1
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FRFT_Ozaktas
这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序,FPGA是Xilinx的virtecx-5,这是我在做毕业设计的时候自己编写的,希望能对你有帮助!(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)
- 2021-03-12 10:49:25下载
- 积分:1
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juchibo
用vhdl语言生成锯齿波,数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)
- 2011-12-21 19:29:51下载
- 积分:1
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8051core-Verilog
8051core-Verilog FPGA
- 2021-02-02 21:59:59下载
- 积分:1
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总结设计中的重点及注意的地方,常出现错误的地方等。
总结设计中的重点及注意的地方,常出现错误的地方等。-Summarize the design of the focus and attention of local, often the wrong place and so on.
- 2022-08-24 04:12:36下载
- 积分:1
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Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计,
内有全套源码以及图片,内容详尽,绝对真实可靠!(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分:1
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ahb_verilog_design
代码为ahb interface ,用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)
- 2020-12-21 14:49:07下载
- 积分:1
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d ,t flip flop
该程序是在d,t,jk触发器上用vhdl语言编写的
- 2022-08-23 17:17:57下载
- 积分:1
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01_基于ZYNQ的FPGA基础入门
说明: VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分:1
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FPGA按键延时模块 debounce
说明: FPGA按键延时模块,产生key_value和key_flag
可直接例化调用(The key delay module of FPGA)
- 2020-06-22 04:20:02下载
- 积分:1