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FPGA
用Vrilog产生一个混沌信号,并用MATLAB仿真,画出波形。(With Vrilog generate a chaotic signal simulation using MATLAB, draw the waveform.)
- 2012-11-15 20:29:35下载
- 积分:1
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新建文件夹 (3)
说明: 对温湿度采集芯片进行配置并且把读到的温度数据显示到数码管上(The temperature and humidity acquisition chip is configured and the temperature data read is displayed on the nixie tube)
- 2020-06-30 22:23:15下载
- 积分:1
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FPGA编程:基于Verilog实现的DDS波形发生器
用FPGA实现DDS波形发生器。可以实现方波,三角波,正弦波的切换,实现频率的调节。三角波和正弦波均用查表法实现。本文档包括一个主程序的代码,按键和显示的实例化程序代码、调用ROM生成的代码以及正弦波和三角波实现的数据表。
- 2022-01-26 05:31:12下载
- 积分:1
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emif_tt
实现dsp与fpga的emif的verilog异步实现,可实现异步读写以及相应功能模块控制,文件中包含仿真后的波形图形以及仿真测试程序,运行环境quartus ii11.0,仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分:1
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UART的FPGA代码
串口代码,FPGA实现,可以直接给出结果,可以仿真并实现
- 2022-03-14 11:01:41下载
- 积分:1
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i2c
说明: 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准,以主机模式与外围设备进行数据通信,对IIC从机模型进行读/读,读/写,写/写,写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失,自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分:1
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s5pv-u-boot-LCD-display
s5pv-u-boot-2011.06之增加LCD显示功能(s5pv-u-boot-2011.06 Increase LCD display function)
- 2013-03-14 09:45:18下载
- 积分:1
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基于 FPGA 的 VGA
本代码是基于可编程门阵列flield视频图形阵列实现。该代码是使用Verilog
- 2022-03-22 21:24:07下载
- 积分:1
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20080931
Design approach for VHDL and FPGA Implementation of
Automotive Black Box using CAN Protocol
- 2009-10-23 00:20:47下载
- 积分:1
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VHDL_Snake_Game
在FPGA开发板上用VHDL语言实现了贪吃蛇游戏,开发软件为quartus 2.这是详细的实验报告,包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)
- 2012-06-25 16:15:26下载
- 积分:1