color bar 彩色条纹的verilog实现

用Verilog实现的16位进位先行加法器。实现了饱和算法。

VESA CVT视频参数计算器，输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)

说明：  用verilog编写的ddr3芯片读写控制程序，经过调试的，可以直接拷贝。已在Xilinx Spartan6 FPGA调试验证。(The ddr3 chip read-write control program written in verilog can be copied directly after debugging. Tested and verified on Xilinx Spartan6 FPGA.)

用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

利用FPGA硬件编程语言Verilog实现USB通信开发(Realization of USB communication development by using FPGA hardware programming language Verilog)

说明：  为串口收发器以及汉明编码，将电脑通过串口发送的7位数据转化成汉明码显示于led上，或把接收到的11位汉明码解码并验错纠错(For the serial port transceiver, and Hamming codes, the computer through the serial port into 7-bit data displayed on the led on the Hamming code, or to receive the 11 Hamming code error correction decoding and experience)

说明：  Protel中VHDL设计参考,pdf,不错的一本学习VHDL的书(Protel design in VHDL)