verilog 串口多字节发送程序

sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)

简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

华为公司学习verilog的资料，绝密资料，想学习verilog编程，想学习FPGA，想以后进华为公司的都可以看看。(Huawei learning verilog information, confidential information, want to learn verilog programming, want to learn FPGA, think later into the Huawei can see.)

本设计旨在实现一种硬件解码模块，这种解码针对ASN.1基本编码规则下的APDU的数据。这种解码模块可以应用在符合GB61850-8-1和GB61850-9-2标准下的GOOSE和SV的MAC层 帧的解码。          本设计亦可以解码通用的ASN.1基本编码规则下的TLV数据流。数据的TAG要求值不大于30，数据的长度范围为1≦LENGTH≦2047，TLV的层级结构不大于4级，整体的数据长度不大于2047。如果需要更大的解码能力则需要修改设计以满足需求。

FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)

QPSK调制，QPSK仿真误码率,QPSK理论误码率 , QPSK仿真误比特率 , QPSK理论误比特率 (QPSK modulation, the signal-to-noise ratio)

基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6)