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multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分:1
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fpgaaverilogamaxamin
verilog 编写的比较最大值最小值得的程序,而且能够求出最大最小值在ram中存储的位置,测试通过下载即用(Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values can be obtained is stored in ram position, the test that is used by downloading)
- 2013-06-06 15:44:48下载
- 积分:1
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adc_cfg
说明: adc器件ads62p49配置代码,已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)
- 2020-11-04 16:29:51下载
- 积分:1
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8 bit general purpose microprocessor verilog code
它是一种以地址总线数据总线为结构的8位微处理器,主要由两部分组成:一是控制单元,数据通路控制单元控制微处理器的所有块、寄存器和部件,数据通路由地址和数据通路信号处理组成指令读写加法;
- 2022-02-01 07:53:18下载
- 积分:1
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遥控器接收解码电路
设计遥控器接收解码电路。该电路接收编码后的串行数据,解码输出数据。电路接收
到的串行数据的格式为: 4 位同步码“ 1010”, 4 位数据(高位在前), 1 位奇校验码(对前 8 位数据校验)(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))
- 2017-11-27 15:10:34下载
- 积分:1
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可综合的Verilog语法和语义,从大学教师cambri…
《可综合的Verilog语法》国外著名大学老师编写,对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
- 2022-03-31 07:34:29下载
- 积分:1
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teal_user
user guide for teal and truss for system verilog
- 2010-04-09 04:40:28下载
- 积分:1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分:1
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mallet algirithm
FPGA(现场可编程门阵列)在医疗系统中得到广泛的接受
- 2022-01-26 04:06:00下载
- 积分:1
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f_adder
一位加法全加器,可以实现低位进位输入和高位进位输出。(full adder)
- 2009-12-24 15:40:39下载
- 积分:1