P4.向量的p范数:‖lbx可以证明当γ趋向∞时,p-范数趋向∞范数例.7第一章引言定理1.2.2(向量范数的等价性)设llll是Rn上的任意两种范数,则存在常数1,C2>0,使得xlls≤lac|t≤c2|rl,∈R”例如ls≤lll≤mlls,vx≤R"几种常用的矩阵范数(A∈R"nx").4的Frobenius克数:‖4=、∑aP2.A的行范数:‖Ax-max∑向a3.A的列范数:‖4|1=max4.A的2范数(谱范数):‖A4|2-√入ma2(A47A),其中max(4A)表示A7A的最大特征值定义1.2.6(矩阵算子范数)x∈R",A∈Rxn,给定一个向量范数川ll(如=1,2,∞,相应的定义矩阵范数ALv=maIAcll称‖A|,为Rxm上的A的算子范数注:它满足(1)|Ax|≤‖A|,(2)|lA|-|alA,va∈(3)三角不等式A4+B≤‖A|+|B|,(4)‖AB≤‖AB|四、序列的极限定义1.27设{x()}为R的向量序列。若对于任意的ε>0,存在正整数K>0,使得当k>K时,有|(8)-洲0,使得对于任意的k有|)川0,存在正整数K>0,使得当k,l>K时,有|x()-xO川<,称序到{x()}为Cauchy点列即k,充分大时,x(8)和x()靠得充分的近定理124Cauchy点列必有极限从而Cauchy点列的聚点就是极限点,它是唯一的定义1.2.10设S是Rη的子集。若S中每个收敛序列的极限都属于S,称S为闭集.若对于任意的∈S,存在一个x的一个邻域N(x,)={x:l|-l P4.向量的p范数:‖lbx可以证明当γ趋向∞时,p-范数趋向∞范数例.7第一章引言定理1.2.2(向量范数的等价性)设llll是Rn上的任意两种范数,则存在常数1,C2>0,使得xlls≤lac|t≤c2|rl,∈R”例如ls≤lll≤mlls,vx≤R"几种常用的矩阵范数(A∈R"nx").4的Frobenius克数:‖4=、∑aP2.A的行范数:‖Ax-max∑向a3.A的列范数:‖4|1=max4.A的2范数(谱范数):‖A4|2-√入ma2(A47A),其中max(4A)表示A7A的最大特征值定义1.2.6(矩阵算子范数)x∈R",A∈Rxn,给定一个向量范数川ll(如=1,2,∞,相应的定义矩阵范数ALv=maIAcll称‖A|,为Rxm上的A的算子范数注:它满足(1)|Ax|≤‖A|,(2)|lA|-|alA,va∈(3)三角不等式A4+B≤‖A|+|B|,(4)‖AB≤‖AB|四、序列的极限定义1.27设{x()}为R的向量序列。若对于任意的ε>0,存在正整数K>0,使得当k>K时,有|(8)-洲0,使得对于任意的k有|)川0,存在正整数K>0,使得当k,l>K时,有|x()-xO川<,称序到{x()}为Cauchy点列即k,充分大时,x(8)和x()靠得充分的近定理124Cauchy点列必有极限从而Cauchy点列的聚点就是极限点,它是唯一的定义1.2.10设S是Rη的子集。若S中每个收敛序列的极限都属于S,称S为闭集.若对于任意的∈S,存在一个x的一个邻域N(x,)={x:l|-l
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最优化参考讲义(上海交大参考讲义)

于 2020-06-05 发布
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详细介绍了最优化方法,是学习最优化的比较好的参考讲义第一章引言第一章引言§1.1最优化问题概述学科简述最优化理论与方法:研究某些数学上定义的问题的最优解,即对于给出的实际问题,从众多的方案中选出最优方案。最优化是一门应用性很强的年轻学科。比如:●工程设计中怎样选择参数,使得设计既满足要求又能降低成本;资源分配中,怎样的分配方案既能满足各方面的基本要求,又能获得好的经济效益:生产计划安排中,选择怎样的计划方案才能提高产值和利润;·原料配比冋题中,怎样确定各种成分的比例才能提高质量、降低成本,最优化问题分类最优化问题分类表分类标志变量个数变量性质约束情况极值个数日标个数函数关系问题性质时间单变量连续无约朿单峰单目标线性确定性静态类型离散随机性多变量函数约束多峰多日标非线性模糊性动态比如:线性规划,非线性规划,随机规划,非光滑规划,多目标规划,整数规划,工作步骤:用最优化方法解决实际问题,一般经过下列步骤1.提出最优化问题,收集有关数据和资料2.建ν最优化问题的数学模型确定变量,列出目标函数和约束条件;3.分析模型,选择合适的最优化方法4.求解,一般通过编制程序,用计算机求最优解5.最优解的检验和实施上述5个步骤常常相互支持、相互制约,在实践中反复交叉进行。模型的三要素:1.变量:最优化问题中待确定的某些量;2.约束条件:求最优解时对变量的某些限制,包括技术上的约束、资源上的约束和时间上的约束等,用等式、不等式、或可行集表示;1.1最优化闩题概述3.目标函数:最优化评价标准的数学描述,一般用最大或最小表示。最优化方法:解析法,直接法,数值解法,二、线性与非线性规划问题例1.1.1[食谱问题设市场上可以买到n种不同的食品,每种食品含有m种营养成分.每单位的笫j种食品售价为c;,且含有第种营养成分为a;设每人每天对第种营养成分的需求量不少于b;,试确定在保证营养的要求下的最经济食谱建立数学模型(1)根据问题的需要设置变量:设每人每天需要各种食品的数量分别为x1,…,xn(2)用所设置的变量把所追求的目标和听受的约束,用数学语言表述出来,得该问题的数学模型:(1.1.3)这里a11表示购买了x;个第种食品所包含的第种营养量,其中min是 minimize的简写,读作“极小化”,s.t.是 subject tol的简写,读作“受限制于”或“约束条件是”。(1.1.1)称为日标函数,(1.1.2)-(1.1.3)称为约束条件例1.1.2[资金使用问题]设有400万元资金,要求4年内使用完,若在一年使用资金x万元,则可得到效益√万元(效益不能再使用),当年不用的资金可存入银行,年利率为10%。试制订出资金的使用规划,以使4年效益总和为最大。显然,不同的使用方案取得的效益总和是不同的。如(1)第一年就把400万元全部用完,则效益总和为√400=20.0(万元)(2)若前三年均不用而存入银行,则第四年把本息和:400×(1.1)3=532.4(万元)全部用完,则效益总和为√52.4-23.07(万元),比第一方案效益大3万元多;(3)若运用最优化方法,可得如下最优方案第年第二年第三年第四年现有资金400342265.1152.8使用金额86.2104.2126.2152.8第一章引言效益总和为√86.2+√104.2+√126.2+√152.8=43.1(万元),是第方案效益总和的两倍多。建立数学模型:设变量x(i-1,2,3,4)分别表示第所使用的资佥数。所追求的目标-4年的效益总和最大,表为+√3+所受到的约束为每年的使用数额既不能为负数又不能超过当年资金拥有数,即第一年00,存在正整数K>0,使得当k>K时,有|(8)-洲0,使得对于任意的k有|)川0,存在正整数K>0,使得当k,l>K时,有|x()-xO川

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BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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