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dds32_1
说明: 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分:1
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hdb3_codedecode
说明: 用VERILOG实现的,hdb3编码器和解码器,经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)
- 2021-04-22 15:58:49下载
- 积分:1
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vhdl 加法器 vhdl 加法器
vhdl 加法器
vhdl 加法器 vhdl 加法器
vhdl 加法器-vhdl adder vhdl adder vhdl adder
- 2022-09-01 23:25:03下载
- 积分:1
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A4_Led3
说明: led学习控制l44444444444444(led verilog led ccccccc)
- 2019-05-06 09:38:14下载
- 积分:1
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pwm
实现pwm波的输出,按键可调占空比的,可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes
)
- 2020-12-20 21:19:08下载
- 积分:1
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数字点阵赛车
数字电路点阵赛车,分为开始前5秒倒计时,59秒计时,赛车显示,赛道显示,失败提示,成功提示,移动控制以及总控制等8个模块。实现由3个开关控制点阵赛车在设置好的赛道中前进或左右移动。
- 2022-04-10 09:21:03下载
- 积分:1
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FSK_FPGA
FSK模拟信号源,利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)
- 2009-07-16 17:09:07下载
- 积分:1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分:1
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Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
- 2022-02-12 19:56:59下载
- 积分:1
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PIC16系列单片机的Verilog描述的完整性
完整的PIC16系列单片机verilog描述-A complete description of PIC16 series of microcontrollers verilog
- 2022-07-23 07:13:49下载
- 积分:1