FPGA

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

说明：  用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)

vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl　adder vhdl　adder vhdl　adder

说明：  led学习控制l44444444444444(led verilog led ccccccc)

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

数字电路点阵赛车，分为开始前5秒倒计时，59秒计时，赛车显示，赛道显示，失败提示，成功提示，移动控制以及总控制等8个模块。实现由3个开关控制点阵赛车在设置好的赛道中前进或左右移动。

FSK模拟信号源，利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)

vhdl um teste com muita coisa interessante ae pra ver

Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)

完整的PIC16系列单片机verilog描述-A complete description of PIC16 series of microcontrollers verilog