程序采用VHDL：频率合成DDS主要调用LPM，

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

用fpga芯片使用vhdl语言对AD转换芯片ADC0809进行控制(Using the fpga chip use language of VHDL AD transform chip ADC0809 control)

VHDL CODE FOR SQUARE WAVE GENERATOR

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

说明：  数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)

不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！()

一个LED大屏幕接收卡的完整设计工程,有需要学习LED大屏幕控制的朋友可以参考

verilog写的LnE算法，可用于计算指数和对数(Verilog written in LnE algorithm, can be used to calculate the index and the logarithm)

大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.

在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)