程序采用VHDL：频率合成DDS主要调用LPM，

Advanced FPGA Design Architecture, Implementation, and Optimization

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

Cypress USB 的主从FPGA 控制实现代码(USB controller)

VHDL code for converting BCD to Decimal

Xilinx FPGA block RAM reconfig via JTAG

包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project

简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))

华为_大规模逻辑设计指导书，看看人家是怎么管理FPGA编程的，真的获益匪浅-Huawei _ large-scale logic design guide book, take a look at how the management of people FPGA programming, and really benefited from