VEROLOG的重要PPT资料,对初学者非常有益处

rebuild file in check for

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

VHDL实现交通灯-VHDL traffic lights

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

vhdl code for internet interface

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx

FPGA，用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

本文介绍了汉明编码与译码通过FPGA器件来实现，介绍了使用VHDL语言编程的基本算法！-This article describes the Hamming encoding and decoding through the FPGA device to implement, introduced the use of VHDL programming language is the basic algorithm!