本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。...

包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.

频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)

basic verilog code on siso, piso, sipo

8b10b编码方式，verilog语言实现，有测试程序。能成功编码。没有环回验证，读者可自行编写环回验证测试程序。(8b10b encoding, verilog language, test procedures. Successful encoding. No loopback verification, readers can write your own loopback verification test procedures.)

URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha

程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM

The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)

本文描述了fpga中的亚稳态时如何产生的，以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。-This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use