本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。...

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

用VERILOG语言编写的电子琴程序.用GW48教学实验箱仿真的-Using Verilog language organ procedures. GW48 teaching experiment with simulation boxes

SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

说明：  简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

在这个项目中我们使用 DE2 115 板上显示每次通过转移在左边按下某个键滚动你好。 这种架构使用管道和多路复用器

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count )

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

ram 64KB designed by haneesh in verilog