ECC密码体制在VHDL

VHDL编写的4个led灯循环明暗变化，通过改变波形占空比实现，课堂作业自编程序-VHDL prepared by the four led lights cycle shading changes, by changing the waveform duty cycle to achieve, self-compiled class operating procedures

说明：  fpga配置锁相环完整程序，使用quartus IP核，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

说明：  用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)

串口程序，基于VHDL 的，很好的程序 快下吧-Serial procedures, based on VHDL, and a very good program, are you fast

[数字通信同步技术的MATLAB与FPGA实现——AlteraVerilog版]书中资源代码，非常好，分享， 希望大家下下！( U651 u0B3 u09108 u09108 u0103 u0101 u7801 uFF0C u975E u5HR U597D uFF0C u5206 u4EAB uFF0C u5E0C u671B u5927 u5BB6 u4E0B u4E0B uFF01)

基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)

VHDL 的100例程代码，能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;