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1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES...
1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-04-30 11:01:06下载
- 积分:1
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21452547
加减可控制的十到十六进制计数器。完全准确,可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)
- 2016-01-11 12:46:04下载
- 积分:1
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alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分:1
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T13_USB
本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输,实现了pc端接收来自FPGA开发板的数据,并显示条纹,具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)
- 2011-01-05 15:10:38下载
- 积分:1
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verilog_curr_design
说明: 实现中采用 Verilog HDL 描述、 ModelSim 进行功能仿真、 Quartus II 进行逻辑综合和适配下载(Design of table tennis game machine)
- 2020-07-16 21:49:36下载
- 积分:1
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xilinx 开发板程序,LED灯控制程序
xilinx 开发板程序,LED灯控制程序-Xilinx development board procedures, LED lamp control procedures
- 2022-08-08 23:14:07下载
- 积分:1
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VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
- 2022-01-20 23:11:51下载
- 积分:1
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NiosII _练习_ ver3 NiosII for旋风,这3。
NiosII_Exercises_Ver3,this niosII 3.o for cyclone
- 2023-08-22 22:50:04下载
- 积分:1
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ICAP_FPGA_Multiboot
在xilinx的ml507板子上用的ICAP功能 配置存储器 这里边包含了控制程序 以及配置ICAP寄存器的程序 就是完整的通过串口控制FPGA多重配置的程序 用verilog实现的(how to configure the ICAP)
- 2021-03-05 15:49:31下载
- 积分:1
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pll
说明: fpga配置锁相环完整程序,使用quartus IP核,Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分:1