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Code VHDL for control VGA FPGA: Xilinx, Altera

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))

uvm验证方法学入门。step by step，适合IC验证人员入门(uvm verification methodology started. step by step, for IC verification personnel entry)

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)

主要介绍，I2C总线主设备发送数据给从设备，代码实现是用Verilog语言实现的，对硬件设计者有很大好处(Introduces, I2C bus master to send data to the slave device, code is implemented in Verilog language, the hardware designer of great benefit)

一个AD9226芯片的驱动，用FPGA写的。虽然简单，但是希望对各位有帮助(An AD9226 chip driver, FPGA written. Though simple, but I hope you will help)

时钟输入：在每个时钟的正沿或负沿对数据进行处理 联合开发网 - pudn.com