altera公司cycloneII全系列说明书，实用

walsh码，在CDMA系统中经常使用到的方法，在quartusII环境下实现的。(walsh code in the CDMA system, the method often used in quartusII environment to achieve.)

说明：  用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证-Traffic lights controller VHDL design, can be controlled by traffic lights at the crossroads of the conversion, through the target chips EPF10KLC84-4 verification

1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.

用于单片机的adc采集实验，经过降噪处理，结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)

用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip

它是一种以地址总线数据总线为结构的8位微处理器，主要由两部分组成：一是控制单元，数据通路控制单元控制微处理器的所有块、寄存器和部件，数据通路由地址和数据通路信号处理组成指令读写加法；

vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang

4选1数据选择器，有使能端控制，4个数据输入，2个地址端，1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)