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FPGA读写SDRAM的VHDL程序(已经测试过)
FPGA读写SDRAM的VHDL程序(已经测试过)-SDRAM read and write the VHDL program FPGA (already tested)
- 2022-05-20 21:52:20下载
- 积分:1
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Verilog-learning-experience
初学学习verilog的经验,可以帮助新手以正确的思维方式,学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分:1
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Single-CPU
说明: 简单的单周期CPU设计,实现的指令有:算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分:1
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count16
说明: 制作16位流水灯,实现LED模块对于拨杆0和1的识别(Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module)
- 2020-06-24 01:20:02下载
- 积分:1
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周立功sopc教程的视频资料,适合广大自学者学习
周立功sopc教程的视频资料,适合广大自学者学习-ZLG sopc video tutorial is suitable for the general self-learners to learn
- 2022-02-06 20:02:55下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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sb133
Based on SVPWM three-level inverter matlab simulation, It describes the application of load forecasting, EULER numerical analysis method.
- 2017-08-28 20:49:27下载
- 积分:1
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Bayer2RGB
Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
- 2020-12-14 15:29:15下载
- 积分:1
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32位元浮点数加法器,用于以VHDL编写的32位元CPU
32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
- 2022-10-08 15:20:02下载
- 积分:1
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本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程,作为我这一段
时间自学 FPGA/CPLD 的总结,如果有什么不正确的地方,敬请各位不幸...
本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程,作为我这一段
时间自学 FPGA/CPLD 的总结,如果有什么不正确的地方,敬请各位不幸看到这篇文章的
大侠们指正,在此表示感谢。当然,这是一个非常简单的时序逻辑电路实例,主要是详细
描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1;
Altera 公司出品的 Quartus II 4.2;Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
- 2022-02-28 11:38:34下载
- 积分:1