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基于Nios II开发板的VGA控制器的DE1控制…
基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态,需要写一个Avalon 从端口响应CPU的控制信号,继而控制整个模块的运行,-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control signal, and then control the operation of the entire module,
- 2023-07-07 19:50:03下载
- 积分:1
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六个数码码动态扫描接口程序,用VERILOG语言编写的
六个数码码动态扫描接口程序,用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language
- 2022-03-24 21:40:23下载
- 积分:1
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shizhong
VHDL写时钟,分频模块什么,实现计时。定点报时,定点闹钟,显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分:1
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5_lcd_ST7565P_12864
液晶ST7565P_12864驱动,实现打点成图。(LCD ST7565P_12864 drive, dot mapping.)
- 2012-04-04 20:01:42下载
- 积分:1
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DS1302
说明: 本代码是控制DS1302的VHDL代码,浅显易懂,方便修改,注意看data sheet,保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)
- 2020-10-22 14:57:23下载
- 积分:1
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flv的vhdl教学文件:在线调试
自己慢慢欣赏吧
flv的vhdl教学文件:在线调试
自己慢慢欣赏吧-flv file of VHDL Teaching: Online debug their慢慢欣赏吧
- 2022-05-22 02:55:52下载
- 积分:1
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fpga_ofdm
这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用,大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)
- 2007-06-13 00:02:43下载
- 积分:1
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RS_Encode_Decode
RS(255,223)编解码算法。verilogHDL代码实现,在XILINX的芯片上得到验证。不包含任何IP核,方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
- 2016-01-21 12:07:34下载
- 积分:1
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SONY公司出品的黑白CCD(44万像素)ICX229的驱动信号产生程序
SONY公司出品的黑白CCD(44万像素)ICX229的驱动信号产生程序-SONY company produced black-and-white CCD (44 megapixels) ICX229 the drive signal generation process
- 2022-04-17 08:51:11下载
- 积分:1
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8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4...
8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
- 2023-07-28 13:55:03下载
- 积分:1