四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL...

uart接收模块 // 波特率：9600 // 数据位：8 // 停止位：1 // 校验位：0(UART receive module Baud rate: 9600 / / / data: 8 / / stop: 1 / / check digit: 0)

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

This free cpu-ip! use verilog

BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)

说明：  FPGA按键加蜂鸣器实验： 加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)

this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.

本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type

实现QAM调制功能和QAM解调功能的代码.(Realize QAM modulation function and QAM demodulation function code.)

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)