这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

FPGA开发全攻略，工程师创新宝典，由张国斌等书写-FPGA development

axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.

SOPC基于MATLAB与DSP Builder设计技术 实验使用说明，非常详细，易于上手(dsp builder)

Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.

用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.