8051Core的源代码，Verilog编写，包括ALU、存储器、SP、dptr等诸多模块，十分完整。

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

使用verilog HDL语言进行编写，通过FIFO缓存，使用uart串口，与上位机进行通信。在本示例中，FPGA向上位机发送的数据每次加一，并在串口调试助手中显示，可以观察相关现象。

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.

应用背景大多数Zedboard平台创造巨大的项目为示范能力Zedboard。本设计实现了全合成，证明目标Zedboard工作。它集锦GPIO模块和所有的默认命名的单主机双奴隶配置的AXI总线的公约。实例化一块Xilinx互连标准复位块。关键技术新的FPGA的发展发生所有的时间。本设计的基准电流软件Xilinx和Vivado工具自动化。Tcl脚本是不包括在内，用户精通当前工具能够从源中提取数据流。在赛灵思WebPACK创建的项目，而是一个开端的用户可以在伊拉降看信号发送到GPIO块学习互连IP

很好的fft学习程序感兴趣的同学可以看哈，下载一下。(it is very good )

设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)

TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)

这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位

说明：  基于FPGA的USB接口设计，实现了USB与FPGA的通信(USB interface to FPGA-based design, implementation of the USB communication with the FPGA)