uartfifo使用fifo进行uart通信

说明：  对于有经验的用户和新用户写的，这本书给您的Verilog HDL的广泛报道。该书强调了实际设计和验证的角度，而不是只注重Verilog的语言方面。(Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. )

this program is a simulation for Aloha

SPI slave接口协议，基于verilog，调试可用

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

QAM调制，解调matlab代码，包含BPSK，QPSK,16QAM,64QAM,256QAM,1024QAM,4096QAM。其中调制方式。代码通过验证。(QAM modulator,demodulator)

我写的 verilog 8 位阵列乘法器。接受两个 8 位数字，并给出 16 位的结果。

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)