uartfifo使用fifo进行uart通信

TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)

好用的SDRAM控制器，经过FPGA平台验证过。(It is a SDRAM controller with verilog code. It is a good code, and confirmed.)

this is the vhdl code for the arithmetic logic unit.enjoy!

采用Verilog语言，实现db8小波分解(Realizing wavelet decomposition)

quartus ii项目文件包，功能是改进的booth乘法器，节省时钟，已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)

AHB to Wishbone memory interface VHDL source code

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

is61lv25616简单的verilog程序，完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)