uartfifo使用fifo进行uart通信

I2C verilog files. Define a simple interface of I2C.After testing to ensure the using.

01 线性调频信号的卷积功能测试（匹配） 02 LFM一维距离像 03 MATLAB联合FPGA仿真输入/输出功能测试 04 解速度模糊 05 扩展目标检测(01 LFM Test function of "conv" 02 LFM Range 03 MATLAB and FPGA 04 resovle speed resolution 05 Extended moving target)

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

利用FPGA实现QPSK数字调制。编程采用Verilog HDL语言。(By using the FPGA realization of QPSK digital modulation. Use Verilog HDL language programming. )

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

ＵＣ1698Ｕ驱动160*160ＬＣＤ中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)

数字ic设计，二级缓存，格雷码，深度256，(Digital IC design, two level cache, gray code, depth 256.)

OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)

verilog编写的uart发送模块，起始位，数据位，可选择的奇偶校验位，停止位。仿真可用

4x4鍵盤使用語法為VHDL，基於cyclone(4 x 4 keyboard using VHDL)