登录
首页 » Verilog » baugh wooley codes

baugh wooley codes

于 2023-06-03 发布 文件大小:1.18 kB
0 1012
下载积分: 2 下载次数: 1

代码说明:

这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • rd1020
    Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.
    2010-07-30 16:51:31下载
    积分:1
  • uart code dsdlab with my clock code
    uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。
    2022-09-14 16:00:03下载
    积分:1
  • 实验17 ADC实验
    鉴于stm32在keil平台上的ADC采集转化,在LCD屏上显示程序(voltage acquisition adc)
    2020-06-20 12:40:02下载
    积分:1
  • pulse_change
    用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)
    2005-07-24 11:53:57下载
    积分:1
  • agc_gen
    AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design )
    2015-04-14 01:16:13下载
    积分:1
  • HDB3
    用Verilog HDL语言进行HDB3编码,并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
    2020-11-30 11:19:28下载
    积分:1
  • cpu110
    基本功能的cpu,自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)
    2016-04-25 10:13:26下载
    积分:1
  • Verilog-Generator-of-Neural-Networks
    利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)
    2018-11-22 15:26:05下载
    积分:1
  • pinlvji
    verilog 简易频率计的设置,包括整个工程(verilog simple frequency meter settings, including the entire project)
    2013-08-18 09:53:52下载
    积分:1
  • 8051corelcd
    fpga上实现的51内核,带有LCD试验,顺利试验成功很好用。(on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.)
    2014-03-30 14:35:20下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载