baugh wooley codes

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.

uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。

鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design )

用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

fpga上实现的51内核，带有LCD试验，顺利试验成功很好用。(on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.)