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rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)

这是Verilog代码使用Verilog实现交叉。

说明：  数字逻辑实验课第十二次作业，基于Verilog的Clock时钟(Clock based on Verilog)

Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能(Verilog HDL language (15,7,2) BCH encoding and decoding functions)

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

说明：  我测试过的！Verilog HDL实现RS编码。(I' ve tested it! RS coding Verilog HDL implementation.)

自己写的一个使用单片机配置FPGA的下位机C代码，使用一个C8051F330,外置SPI FLASH,通过串口可将程序写入FLASH,上电时自动加载到FPGA完成配置。(Wrote it myself, using a microcontroller to configure FPGA code for the next bit plane C, using a C8051F330, external SPI FLASH, the program is written through the serial port can be FLASH, power-on automatically loaded into the FPGA to complete the configuration.)

ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)

SDIO slave, written in verilog, does not support SPI mode.

ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)