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5_lcd_ST7565P_12864
液晶ST7565P_12864驱动,实现打点成图。(LCD ST7565P_12864 drive, dot mapping.)
- 2012-04-04 20:01:42下载
- 积分:1
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EncoderUsingif
encoder using else if statement
- 2015-05-21 13:41:00下载
- 积分:1
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基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习...
基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙,秒,分。
有开始,暂停,复位功能。
学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
- 2022-12-27 19:50:04下载
- 积分:1
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使用LPM_ROM的实际的例子
使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM
- 2022-10-03 13:00:03下载
- 积分:1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分:1
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can-lite-vhdl-master
说明: CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-08-19 04:15:42下载
- 积分:1
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1pps
说明: fpga程序,产生1pps脉冲信号,使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:01下载
- 积分:1
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同步FIFO功能,通过Modelsim仿真Verilog语言描述6…
同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
- 2022-03-24 20:37:31下载
- 积分:1
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demo
NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)
- 2013-07-19 11:17:29下载
- 积分:1