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based on VHDL development mcu with external device interface, mcu solve the high
基于VHDL语言开发的mcu与外部器件的接口程序,解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.
- 2023-06-24 09:15:02下载
- 积分:1
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业界标准的Verilog语法格式
verilog标准语法,还有很多的样例参考,学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分:1
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serial port simulated programme of lattice
lattice的串口仿真的程序- serial port simulated programme of lattice
- 2023-04-29 09:40:03下载
- 积分:1
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pcm
利用VHDL语言和模块化设计实现PCM编译码的功能,整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )
- 2020-11-02 10:39:53下载
- 积分:1
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基于Actel A3P030 FPGA液晶显示器使用jdl12864串行接口,时钟可调
基于Actel A3P030 FPGA,液晶采用JDL12864串行接口,时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
- 2022-07-05 03:00:11下载
- 积分:1
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lvds_ctr_top
说明: 用verilog编写的LVDS接口驱动程序,采用IOSERDES技术实现,经过Spartan6 FPGA调试验证,有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分:1
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FPGA 出租计费器
本代码绝对真实可靠,原用于长沙理工大学EDA课程设计之出租车计费器。本代码在要求的基础上添加显示时速和报警功能。希望此代码对有此需求的同学有所帮助!
- 2022-01-25 20:43:32下载
- 积分:1
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计数器,vhdl,调试通过。
COUNTER 用于xilinx硬件,里面已建工程,修改ucf即可。设计由3部分组成,计数器,100M分配时钟,顶层模块,其中顶层模块包括计数器和分频器。
- 2022-01-22 06:17:06下载
- 积分:1
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AD9826-verilog
使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)
- 2016-05-09 14:45:37下载
- 积分:1
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ACO-OFDM
ACO-OFDM sdakldjas seuekdsjakdnskd
- 2021-04-13 22:58:55下载
- 积分:1