AD0809芯片DA0832程序实现

Verilog code for RS-(255,239) encoder.

说明：  jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

programming of and gate

FPGA扫描LED显示灯，动态扫描,进行流水显示(FPGA Scan LED indicator lights, dynamic scanning, make the water show)

具有先进后出的堆栈功能。此LIFO堆栈具有两个按键（write， read），按下write键后，开始输入数据data0-data3；按下read键后，7段数码管开始倒序显示data3-data0（十进制）。 高级要求（可选）： 按下write键，VGA显示“Write”字样，并同时显示输入数据；按下read键，VGA显示“Read”字样，并同时显示输出数据。

VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)

关于FFT算法的FPGA实现（源码），数字信号处理不可少。-FFT algorithm on the FPGA implementation (source code)

基于basys2的简单的乒乓球小游戏，通过ise13.4开发，使用语言VHDL，能够通过VGA在显示屏显示，能够实现双人对打，有计分功能。(Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.)

ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation

very good code for edge detection based on vhdl programming.