URAT串口调试经典程序（Verilog）

“同步”表示相同频率的时钟源，“ FIFO”表示先进先出的意思。 FIFO 的用 意一般都是缓冲数据，另模块独立，让模块回避调用的束缚。同步 FIFO 是 RAM 的亚 种，它基于 RAM，再加上先进先出的机制，学习同步 FIFO 就是学习如何建立先进先出 的机制。

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)

i2c core : i2c master top

基于PCI的数字信号发生器 关键词：PCI总线，PCI9054，FPGA，卡尔曼滤波器(PCI-based digital signal generator Keywords: PCI bus, PCI9054, FPGA, Kalman filter)