使用FPGA SPARTAN-3E 的ledbanner verilog代码

红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)

early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)

zybo1_FPGA_Design_Flow_using_Vivado，基于zybo实现加法器功能，zybo简单例程。

lite pcie 的程序，参考demo可以用来熟悉pcie axi-lite方式

viterbi decode by verilog

说明：  使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)

VHDL语言实现VGA的显示彩条横条九宫格的功能。(VGA display color of the VHDL language bar Jiugongge function.)

SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)

SPI slave接口协议，基于verilog，调试可用

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )