采用VHDL编写的步进电机控制程序

quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example

An odd parity checker as an FSM using VHDL

说明：  本书从电子技术和通信系统的角度讲解gps接收机的设计开发原理，其内容集中在用户终端，即接收机的设计原理和软件实现上。全书分为两大部分，第一部分为理论篇，第二部分为实现篇。理论篇首先对导航的基本目的进行了阐述，并由一个浅显的二维导航系统对导航信号的特点进行了推导，随后阐述了gps信号格式，同时对于直接影响接收机性能的射频前端部分做了理论分析；实现篇主要对本书实现的软件gps接收机的系统实现和源代码进行了讲解，同时作为总结，将信号处理的结果和有意义的中间变量以图示的方式给出，可以使读者有一个感性的认识，同时提升学习兴趣。. 本书适合从事卫星导航接收机研发的技术人员和卫星通信接收机研究的研究人员，尤其是从事北斗系统研发的专业人员、cdma通信系统研发人员，以及通信电子类专业的高年级本科生和研究生阅读，既可作为教学培训的教材，也可作为相关专业工程技术人员的参考资料。(This book explains the design and development principle of the GPS receiver from the perspective of electronic technology and communication system. Its content focuses on the design principle and software implementation of the user terminal, that is, the receiver. The whole book is divided into two parts. The first part is the theoretical part and the second part is the realization part. Firstly, the basic purpose of navigation is expounded, and the characteristics of navigation signal are deduced by a simple two-dimensional navigation system. Then, the format of GPS signal is expounded. At the same time, the front-end part of radio frequency which directly affects the performance of the receiver is theoretically analyzed.)

Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)

xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)

&单元格

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

（1）用HDL设计一个多功能数字钟，包含以下主要功能：精确计时，时间可以24小时制或12小时制显示； （2）日历：显示年月日星期； （3）能用QuartusII软件仿真；