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FPGA
Verilog学习例程EP2C5,内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)
- 2020-12-06 22:29:21下载
- 积分:1
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CNT60
六十进制计数器,显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)
- 2012-10-17 19:32:56下载
- 积分:1
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cfo_correction
说明: OFDM载波同步,Verilog编写,完全正确!!!(verilog )
- 2020-11-05 21:39:50下载
- 积分:1
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package_control-master
说明: 从github下载的,能够参考设计AXI4的协议接口(AXI4 Verilog template)
- 2019-03-30 16:14:05下载
- 积分:1
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sdram 代码
sdram 代码在最后要强调的是,本专题以技术为主,由于篇幅的原因,不可能从太浅的方面入手,所以仍需要有一定的技术基础作保证,而对内存感兴趣的读者则绝不容错过,这也许是您最好的纠正错误认识的机会!
- 2022-08-23 08:24:46下载
- 积分:1
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textiowrite
quartus ii 环境下,一个完整的利用TEXTIO仿真的源代码,包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分:1
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VGA
VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)
- 2017-12-07 20:55:10下载
- 积分:1
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ste_svpwm
实用Verilog编写的SVPWM程序,产生出SVPWM波形,可用于实现同步电机或者异步电机的空间矢量控制算法。(Practical Verilog of SVPWM written procedures, resulting in the SVPWM waveform can be used to implement the space vector control algorithm of the synchronous motor or induction motor.)
- 2021-04-18 16:58:52下载
- 积分:1
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基于Nios II开发板的VGA控制器的DE1控制…
基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态,需要写一个Avalon 从端口响应CPU的控制信号,继而控制整个模块的运行,-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control signal, and then control the operation of the entire module,
- 2023-07-07 19:50:03下载
- 积分:1
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8_LigWater
FPGA,VHDL语言 :分频1S 8位流水灯,适用于所有FPGA芯片,VHDL源程序!!(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)
- 2012-10-02 11:25:50下载
- 积分:1