dds digital shift Signal Generator, full

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)

说明：  用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

FIR filter up to 128x

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)

LED based video wall tech spec

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

为华为内部文件，用于华为内部员工培训，对我们从事科研的人来说，这是个一个非常好的材料，可以学习华为文档管理规范，和代码编写规范。当然了也学习华为如何化繁为简，让员工迅速掌握关键技术。这个一个非常值得学习揣摩的材料