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CPLD_PWM
一个在CPLD,EPM70128上实现的PWM控制源程序。(A CPLD, EPM70128 realize the PWM control on the source.)
- 2008-07-25 12:43:39下载
- 积分:1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分:1
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ORIGINAL_DOWNLOAD
说明: risc 8 by coonan compatible with PIC16C57
- 2019-12-05 20:32:55下载
- 积分:1
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用VHDL语言实现数字钟的设计
用VHDL语言实现数字钟的设计,要求设计实现一个具有带预置数的数字钟,具有显示年月日时分秒的功能。用6个数码管显示时分秒,set按钮产生第一个脉冲时,显示切换年月日,第2个脉冲到来时可预置年份,第3个脉冲到来时可预置月份,依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒,第 8个脉冲到来后预置结束,正常工作,显示的是时分秒。Up为高电平时,upclk有脉冲到达时,预置位加1.否则减1。
- 2022-10-28 10:35:04下载
- 积分:1
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061110061
在quartus平台下使用verilog语言编程实现简单的单流水线CPU,可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)
- 2010-05-21 20:01:16下载
- 积分:1
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FM_T
一个简单的FM调制模块,FM发射,用Verilog编写,基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)
- 2020-11-25 20:19:32下载
- 积分:1
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vc707-ucf-xdc-rdf0155-rev2-0
vc707 board ucf xdc files
- 2018-06-14 05:50:36下载
- 积分:1
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VHDL_course
VHDL实用教程,详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)
- 2021-04-01 13:29:08下载
- 积分:1
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vhdl_ders_1_temel_bilgiler
VHTL PROGRAMMING COURSE
- 2009-07-11 22:24:59下载
- 积分:1
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拥有VGA彩色信号发生器Verilog ISE环境
自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
- 2023-01-14 23:05:03下载
- 积分:1