这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用...

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

利用dsp builder设计的IIR滤波器，已经验证完全可以使用，只需要把其中系数改变。内含VHDL代码(Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.)

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)

n bit generic shift registers

乘法器功能 直接实现两个数字信号的相乘～-Multiplier features two digital signal direct implementation of the multiplication ~

用VHDL语言实现TDMA编码,简单，明了。看标注就可以看懂-use vhdl langhanTDMA