在ise10.1.3 Xilinx PicoBlaze的应用开发。

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners

verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。(verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。)

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis

matlab code for JTAG cable checking

DDS in our camera design

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)

this is a simulation fm in simulink mathlab this is one program with pll

说明：  serdes中的8B/10B编码 verilog实现(Implementation of 8B / 10B coding Verilog)