CPLD LATTICE1032测试模式代码

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)

Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

Spartan-3E板卡XC2C64A CPLD 的代码(the XC2C64A CPLD on the Spartan-3E Starter Kit boards)

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!

利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)

i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c