音频信号分析仪的FPGA源码

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.

伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)

vc707 board ucf xdc files

任意数据发生器的源代码-arbitrary data source code generator

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--

verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)

This is a divider, which is depicted as well. It is a programming language Vhdl.

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)