音频信号分析仪的FPGA源码

适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)

HDL example source code 1/5 tff_a

Image Embedded VHDL Code by using watermarking technique

Xilinx system generator

FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO

ac97 VHDL core

4 bit convoltion with vhdl.

支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU，verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL