音频信号分析仪的FPGA源码

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

HDLC控制器源码，包括单独HDLC的Tx端和Rx端实现，以及顶层带FIFO和Wishbone总线控制器的实现，通过Wishbone可方便与CPU连接，通过软件控制整个HDLC控制器的工作。

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

用fpga芯片使用vhdl语言对AD转换芯片ADC0809进行控制(Using the fpga chip use language of VHDL AD transform chip ADC0809 control)

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )

DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)

王金明的一些学习VHDL的子-Wang Jinming study of some subset of VHDL

VHDL与源代码包-and VHDL source code