音频信号分析仪的FPGA源码

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

How to Connecting Xilinx FPGAs to the Philips

应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.

用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )

实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )

先用Matlab理论仿真，再用Verilog语言在ISE环境下编写程序，可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)

说明：  AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)

Ethernet MAC-MII interface of Transmit

用VHDL制作的I2C控制器，是一个component,之间添加就可以使用。-VHDL produced using I2C controller, is a component, you can use to add between.

多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card