VHDL采用I2C控制器，是一个组件，你可以使用添加之间。

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)

verilog_ad0809 cpld control

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)

GMSK基带信号的调制解调基于SIMULINK的系统，计算误码率，(Modulation and Demodulation of GMSK Baseband Signal)

一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak

xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise

This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

verilog alu 8bit for engineers