16/64 点 FFT

用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit

FPGA编程实现串口通信，源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.

说明：  经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)

dsp与fpga通信的verilog程序，强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)

说明：  ADC Reference code!Clock 100kHz

贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)

周立功sopc教程的视频资料，适合广大自学者学习-ZLG sopc video tutorial is suitable for the general self-learners to learn

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

对数计算源程序，能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode