build synthesizer on a de2 dev fpga board

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

cpld 控制 8-32M sdram 控制器 maxII epm570实现。 pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation

basic verilog code on siso, piso, sipo

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

通过摄像头图像的提取，在FPGA开发板上实现的，主要实现了图像轮廓的提取(Extraction of the image through the camera, in the FPGA implementation of the development board, the main achievement of the image contour extraction)

单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)

串行加法器的vhdl描述，用两个移位寄存器和一个全加器，一个d触发器实现(The VHDL description of the serial adder, with two shift registers and a full adder, a D trigger)

应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多-By VHDL generating random Numbers, in the application of the fuzzy control simulation

hdb3 using language VHDL(Indoor using VHDL language)

时钟输入：在每个时钟的正沿或负沿对数据进行处理 联合开发网 - pudn.com