build synthesizer on a de2 dev fpga board

AES算法在FPGA上的实现，对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)

层合板的刚度的计算和验算，包括拉伸刚度A、弯曲刚度D以及耦合刚度B。 首先要给定层合板的各个参数，具体有：层合板的层数N；各单层的弹性常数E1、E2、 、G12；各单层对应的厚度；各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)

this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

maxplus2为开发环境 vhdl编写的 键盘 程序-maxplus2 VHDL development environment for the preparation of the keyboard procedures

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

PCI vhdl for Fpga designer to design PCI IP

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output

FPGA UART transmit and so on