Application of VHDL language of the control procedures of traffic lights. Famili...

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

说明：  fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现(FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve)

4x4键盘模块。这个文件包括普通的键盘设计方案说明和相关的原程序。-4x4 keyboard module. The documents include ordinary keyboard design program descriptions and procedures related to the original.

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)

实现一个售票系统显示牌的设计，使用8位拨码开关输入车次，按键A按下一次表示该车次售出一张票，同时数码管显示该车次（K+3个数码管显示拨码开关对应的十进制数，如拨码开关值为”00010101”时，则车次为 “K021”）及该车次剩余的票数(每车次总票数值为100)，若K021次车还剩余78张票，则数码管显示“K021-78”。要求至少存储3趟车次信息，例如车次K020，K021，K022 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

说明：  fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)