vhdl 基于cpld的8*8点阵显示显示心型

用verilog状态机实现的自动售货机，是一次课程作业，参考了网上的例子进行了修改(Automatic vending machine implemented with Verilog state machine)

ep2c5 实现 段寄存器,实验一 verilog语言，quartus 2 仿真-Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw

以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn

基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)

FFT implementation using C program

用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

说明：  FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

Disparity mapp code in VHDL