vhdl 基于cpld的8*8点阵显示显示心型

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!

基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM

Implement the 7 segment diplay on spartan 3

Xilinx FPGA moving data across asynchronous clock boundaries

本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)

matlab 并行程序parfor用法matlab 并行程序parfor用法(matlab 并行程序parfor具体用matlab 并行程序parfor用法)

带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

adding custom ip EDK

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,